Field of the Invention
The present invention relates to programmable memory devices such as EEPROMs, nonvolatile memory cells, and flash memory cells. More particularly, the present invention is directed to a twin-cell programmable memory cell structure and to a method of fabricating the same.
Flash memory provides non-volatile memory where blocks of flash memory are erasable in a flash operation. Two well-known types of circuitry that are present in flash memory cells are NAND and NOR. There are a variety of device structures employed for flash memory including two well-known structures, stack gate and split gate. Each of these flash memory structures has it""s own inherent strengths and weaknesses associated therewith. A stack gate device, for example, has its channel region covered by a floating gate that is overlapped by a control gate. In a split gate device, a portion of the channel is controlled directly by the control gate, while the remaining portion of the channel is controlled by the floating gate that is modulated by the control gate.
In a conventional high-density, high-speed NOR flash memory, the random access speed is approximately 30 ns, the write speed is approximately 1-10 Âxcexcs, the write/erase endurance is greater than 106 cycles, the data holding time is greater than 10 years and the cell size is about 0.5 Âxcexcm2. In a commonly employed n-type MOS flash memory device, a gate oxide having a thickness of from about 7 to about 12 nm is employed, and the channel has a length of about 0.25 to about 0.5 nm.
There are a variety of programming methods available for programming the flash memory by writing the desired information to the cells of the flash memory. One of the most widely employed methods used in programming flash memory cells is by channel hot-electron injection. In such programming and during a write cycle, the control gate of the cell being written to is biased to a high voltage level of approximately 7 to 9 V, while the source is maintained at ground and the drain is biased to 3 to 5 V.
Another commonly employed programming method which is well known to those skilled in the art is Fowler Nordheim (FN) tunneling. In FN tunneling, a relatively high control gate voltage of about 13 to 20 V is needed, while both of the drain and source gates are tied to ground. The high voltage needed in FN tunneling for writing to the flash memory cell is required to form an electric field of approximately 12 mV/cm which is needed to facilitate tunneling of electrons from an inversion layer in the channel area into the floating gate. For an erasure operation, a voltage as high as 12 V is applied to the source gate for a source gate erase, while the substrate is grounded and the drain gate is left floating. Alternatively, a negative voltage of about xc3xa2xe2x80x38 to about xc3xa2xe2x80x39 V is applied to the control gate, a positive voltage of about 3 to about 5 V is applied to the drain node and the source node is left floating.
Flash memory provides the advantage of maintaining storage of data even when power is removed and performing block data erasure so that a partial or full memory macro can be reprogrammed again after the original data is completely erased. However, flash memory typically suffers from having a relatively slow programming speed (and write speed). In comparison, the random write access time is approximately 1 ns for a state of the art SRAM and approximately 10 ns for a DRAM. Therefore, flash memory is typically employed for storing data for read operations, but not for true high-speed random read/write applications. Once the stored data needs to be altered a relatively long programming time is required.
Flash memory cells typically require that the threshold voltage (Vt) difference between a programmed cell having a state xe2x80x9c1xe2x80x9d and an un-programmed cell having a state xe2x80x9c0xe2x80x9d be minimally 2 V. This relatively high Vt difference is needed for at least the following reasons: (1) most flash memory designs use a direct sensing technique that requires sufficient Vt difference between a programmed cell or an un-programmed cell for sensing; (2) a high Vt difference helps to prevent degradation which results in shortened life-time for the flash memory due to Vt disturbances caused by read, write and erase operations; and (3) when Vt for a programmed cell is not high enough an array formed by a plurality of flash memory cells is subjected to direct current leakage that is large and would not be tolerable for a low-power operation involving low Vt levels.
The programming speed associated with flash memory is relatively slow since it depends upon an amount of time required to store an amount of charge required on the floating gate to produce a high enough Vt to produce meaningful Vt shift when a cell changes from a state xe2x80x9c0xe2x80x9d to a state xe2x80x9c1xe2x80x9d. Typically, flash memory cells are over programmed in order to ensure a uniform Vt of the programmed cells, further increasing the time required to program a cell and decreasing programming speed.
In addition to the above, there are problems typically associated with the accuracy of flash memory cells. Disturbances, such as unintentional voltage coupling by adjacent cells due to read, write, and erase operations, may cause the Vt programmed cells to deviate from the require Vt, generally causing a read or write failure. Flash memory cells having an inherently small size are oftentimes arranged in cross-point array format.
The sensing scheme used for a cross-point array is usually via an open bitline architecture using a single rail direct sensing or dual rail sensing technique, both of which require a reference voltage generator. An insufficient Vt difference may result in a sense margin too small to be reliable, generally causing read and write failure. Furthermore, a marginal sense signal is susceptible to coupling noise, further compromising the data integrity of the flash memory cell. In general, the reliability of the flash memory is limited due to typical inherent sensing limitations associated with a single polarity.
In view of the aforementioned drawbacks with prior art programmable memory cells such as flash memory cells, there is a continued need for providing new and improved programmable memory cells in which the write speed is enhanced without compromising the reliability and durability of the memory cell.
One object of the present invention is to provide a programmable memory cell structure having an array of memory elements, each element having two cells in which the write speed of the memory cell is enhanced.
A further object of the present invention is to provide a programmable memory cell structure having an array of memory elements, each element having two cells in which the write speed is enhanced without compromising the reliability and durability of the memory cell.
A still further object of the present invention is to provide a programmable memory cell structure having an array of memory cell elements, each element having two cells in which storage capacity of the programmable memory cell is increased.
A yet further object of the present invention is to provide a programmable memory cell structure having a reference line that is common to each of the memory cells.
An even further object of the present invention is to provide a programmable memory cell structure in which the wordline of each memory element is formed borderless to the bitline.
A yet even further object of the present invention is to provide a programmable memory cell structure having a plurality of shallow trench isolation regions that are formed self-aligned to the bitline diffusion regions and the floating gate edges.
Another object of the present invention is to provide a programmable memory cell structure in which the bitlines are borderless to the floating gates and the control line.
It is noted that the term xe2x80x9cprogrammable memory cellxe2x80x9d includes EEPROMs, non-volatile memory cells, flash memory cells and other like memory cells that can be programmed by applying a voltage thereto.
These and other objects and advantages are achieved in the present invention by providing a novel twin-cell programmable memory cell structure in which a sidewall gate formation technique is employed that is capable of forming the inventive twin-cell in the same density as a conventional single cell array. That is, the first cell is formed on one sidewall of the control gate, and the other cell is formed on the other sidewall. The two cells of the inventive memory cell structure are symmetrical and are located relatively close to each other. Moreover, each cell of the twin cell is tied to its own bitline; however, both cells are modulated by the same control gate. One important advantage of the inventive twin-cell programmable memory cell structure is that not only is the cell-density unchanged, but also one cell can be used as a reference cell as the other cell is sensing. One aspect of the present invention relates to a pair of programmable memory cells which comprises a shared control gate, first and second floating gates having respective gate regions disposed on respective sides of the control gate, and dielectric structures disposed between said control gate and respective ones of said gates of said floating gates, wherein said control gate and said gates of said first and second floating gates are located within a space of a single lithographic square.
Another aspect of the present invention relates to a pair of programmable memory cells which comprise a single control gate, a first floating gate, a second floating gate, a first bitline, and a second bitline, wherein said control gate is self-aligned to said first and second floating gates.
A still other aspect of the present invention relates to a programmable memory cell layout for a non-volatile memory cell which comprises a programmable memory wordline borderless to a bitline.
A yet other aspect of the present invention is to provide a method for fabricating the inventive twin-cell programmable memory cell structure. Specifically, the method of the present invention includes the steps of:
forming a pair of programmable memory cells in a slot that is present in a pad layer, said pair of programmable memory cells comprising a shared control gate, first and second floating gates having respective gate regions disposed on respective sides of the control gate, and dielectric structures disposed between said control gate and respective ones of said gates of said floating gates, wherein said control gate and said gates of said first and second floating gates are located within a space of a single lithographic square;
removing said pad layer about said slot;
forming first and second bitlines in regions previously occupied by said pad layer; and
forming a wordline that is borderless to said first bitline and said second bitline, wherein said wordline is interconnected to said shared control gate.